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https://github.com/eyantra698sumanto/digital-design-on-fpga
This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
https://github.com/eyantra698sumanto/digital-design-on-fpga
fpga makerchip systemverilog tl-verilog verilog virtual-fpga vsd
Last synced: 1 day ago
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This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
- Host: GitHub
- URL: https://github.com/eyantra698sumanto/digital-design-on-fpga
- Owner: Eyantra698Sumanto
- License: apache-2.0
- Created: 2021-10-19T15:46:55.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2022-07-17T08:13:18.000Z (over 2 years ago)
- Last Synced: 2024-11-11T12:18:59.560Z (2 months ago)
- Topics: fpga, makerchip, systemverilog, tl-verilog, verilog, virtual-fpga, vsd
- Homepage:
- Size: 72.3 KB
- Stars: 3
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Digital-Design-on-FPGA
This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
-----------------------------------------------------------------------------------------------------------------------------------------------
# Contents
- [Introduction](#introduction)
* [Makerchip](#makerchip)
* [Virtual FPGA](#virtual-fpga)
- [Interfacing LEDs](#interfacing-leds)
* [Code and FPGA](#code-and-fpga)
* [Diagram](#diagram)
* [Waveform](#waveform)
- [LED Counter](#led-counter)
* [Code and FPGA](#code-and-fpga-1)
* [Diagram](#diagram-1)
* [Waveform](#waveform-1)
- [Interfacing LEDs Lab](#interfacing-leds-lab)
* [Code and FPGA](#code-and-fpga-2)
* [Diagram](#diagram-2)
* [Waveform](#waveform-2)
- [Interfacing Seven segment](#interfacing-seven-segment)
* [Code and FPGA](#code-and-fpga-3)
* [Diagram](#diagram-3)
* [Waveform](#waveform-3)
- [Interfacing Seven Segment Labs](#interfacing-seven-segment-labs)
* [Code](#code)
* [Diagram](#diagram-4)
* [FPGA](#fpga)
* [Waveform](#waveform-4)
- [Traffic Light lab](#traffic-light-lab)
* [Problem Statement](#problem-statement)
* [Finite State Machine](#finite-state-machine)
* [Code](#code-1)
+ [Code Snippet for NORTH, SOUTH, EAST and WEST](#code-snippet-for-north--south--east-and-west)
+ [Code Snippet for NORTH_Y, SOUTH_Y, EAST_Y and WEST_Y](#code-snippet-for-north-y--south-y--east-y-and-west-y)
* [Diagram](#diagram-5)
* [FPGA Simulation](#fpga-simulation)
- [Acknowledgement](#acknowledgement)
- [References](#references)
# Introduction
## Makerchip
Makerchip is an Open Source App for circuit design, verilog programming, VLSI design, etc. Makerchip provides free and instant access to the latest tools from your browser and from your desktop. This includes open-source tools and proprietary ones. For more detail refer:
https://www.makerchip.com/
## Virtual FPGA
It is an FPGA board that can be simulated using Makerchip IDE. It is very useful to see the simulation of the real FPGA on a desktop. For more details refer:
https://github.com/BalaDhinesh/Digital-Design-on-FPGA--VSDOpen21
# Interfacing LEDs
This topic dealing with interfacing of the LEDs on the Virtual FPGA by writing a System Verilog code in Makerchip.
Please refer the following link for the project:
https://www.makerchip.com/sandbox/0mZf5hwmG/076hWmn#
## Code and FPGA
## Diagram
## Waveform
# LED Counter
Please refer the following link for the project:
https://www.makerchip.com/sandbox/0mZf5hwmG/0j2hyj6
## Code and FPGA
## Diagram
## Waveform
# Interfacing LEDs Lab
Please refer the following link for the project:
https://www.makerchip.com/sandbox/0mZf5hwmG/0lOhzop
## Code and FPGA
## Diagram
## Waveform
# Interfacing Seven segment
A seven-segment display (SSD) is a form of electronic display device for displaying decimal numbers. They can be used as an alternative to complex display's such as dot matrix.
A SSD has 7 segments and theoretically we can use it to display 2^7 = 128 combinations of characters. But most of these combinations, doesn't make sense to a human eye. Decimal numbers can be displayed correctly on a 7 segment panel.
Please refer the following link for the project:
https://www.makerchip.com/sandbox/0mZf5hwmG/0k5hqnm
## Code and FPGA
## Diagram
## Waveform
# Interfacing Seven Segment Labs
Truth table for the BCD to seven segment display:
The Seven Segment Display interfacing is done in this workshop using the Virtual FPGA in Makerchip. A System Verilog code is written in order to describe the functionallity of the seven segment display. A reg is used to store a BCD value and is incremented for every count of the counter and then converted to Seven Segment equivalent using the above truth table.
Please refer the following link for the project:
https://www.makerchip.com/sandbox/0mZf5hwmG/0Wnhyjg#
## Code
## Diagram
## FPGA
## Waveform
# Traffic Light lab
## Problem Statement
## Finite State Machine
This project deals with the Traffic Controller Design using the Makerchip Virtual FPGA. As shown above we are focussing on the Yellow and Green light and these are depicted using the G and D of the 7 segment display respectively. Green light turns ON for 8 clock pulses while Yellow turns on for 4 clock pulses. All lights OFF are considered as Red Signal. The fours 7 segment display are considered as signal for the four ways.
Please refer the following link for the project:
https://www.makerchip.com/sandbox/0mZf5hwmG/0nZh6G5#
## Code
### Code Snippet for NORTH, SOUTH, EAST and WEST
```
NORTH :
begin
// Enable first seven segment and set to Green
digit <= 4'b0111;
segment <= 7'b1110111;
/* TODO: 1. Keep the green NORTH signal active for 8 seconds
2. Set state of signal to yellow NORTH after that
HINT: Use if-else block
*/
if(count==7) begin
assign state=NORTH_Y;
assign count=0;
end
else assign count=count+1;
end
```
### Code Snippet for NORTH_Y, SOUTH_Y, EAST_Y and WEST_Y
```
NORTH_Y :
begin
// Enable first seven segment and set to Yellow
digit <= 4'b0111;
segment <= 7'b1111110;
/* TODO: 1. Keep the yellow NORTH signal active for 4 seconds
2. Set state of signal to green SOUTH after that
*/
if(count==3) begin
assign state=SOUTH;
assign count=0;
end
else assign count=count+1;
end
```
## Diagram
## FPGA Simulation
# Acknowledgement
I would like to thank Mr. Kunal Ghosh, Mrs. Anagha Ghosh, Mr. Steve Hoover and Mr. Bala Dinesh for the tutorial explained in the simplest way possible. It helped me to learn more about the FPGA and Makerchip in a very easy and structured manner. It will be very helpful for students to work on Virtual FPGA as many cannot afford the real one. It is also useful for the simulation purpose.
# References
1. https://github.com/BalaDhinesh/Digital-Design-on-FPGA--VSDOpen21
2. https://www.makerchip.com/
3. https://verilogcodes.blogspot.com/2015/10/verilog-code-for-bcd-to-7-segment.html
4. https://www.geeksforgeeks.org/bcd-to-7-segment-decoder/
5. http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf