https://github.com/eyantra698sumanto/spice-to-verilog-converter

Spice to Verilog Converter
https://github.com/eyantra698sumanto/spice-to-verilog-converter

analog spice system-verilog verilog verilog-hdl

Last synced: 6 months ago
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Spice to Verilog Converter

• Host: GitHub
• URL: https://github.com/eyantra698sumanto/spice-to-verilog-converter
• Owner: Eyantra698Sumanto
• License: gpl-3.0
• Created: 2022-06-03T21:53:16.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2023-05-23T09:08:37.000Z (over 2 years ago)
• Last Synced: 2025-04-05T07:33:08.854Z (7 months ago)
• Topics: analog, spice, system-verilog, verilog, verilog-hdl
• Language: Python
• Homepage:
• Size: 23.4 KB
• Stars: 12
• Watchers: 1
• Forks: 1
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# spice2verilog

This is a Spice to verilog converter.