https://github.com/eyantra698sumanto/xor-xnor-gate
https://github.com/eyantra698sumanto/xor-xnor-gate
Last synced: 4 months ago
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- Host: GitHub
- URL: https://github.com/eyantra698sumanto/xor-xnor-gate
- Owner: Eyantra698Sumanto
- License: gpl-3.0
- Created: 2022-03-02T14:12:00.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-07-17T08:14:55.000Z (almost 3 years ago)
- Last Synced: 2025-01-09T16:03:11.389Z (5 months ago)
- Language: Verilog
- Size: 3.78 MB
- Stars: 4
- Watchers: 1
- Forks: 12
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Mixed Signal Circuit Design and Simulation Marathon
# XOR-XNOR-Gate
- [Abstract](#abstract)
- [Reference Circuit Diagram](#reference-circuit-diagram)
- [Reference Waveform](#reference-waveform)
- [Circuit Details](#circuit-details)
- [Truth Table](#truth-table)
- [Software Used](#software-used)
* [eSim](#esim)
* [NgSpice](#ngspice)
* [Makerchip](#makerchip)
* [Verilator](#verilator)
- [Circuit Diagram in eSim](#circuit-diagram-in-esim)
- [Verilog Code](#verilog-code)
- [Makerchip](#makerchip-1)
- [Makerchip Plots](#makerchip-plots)
- [Netlists](#netlists)
- [NgSpice Plots](#ngspice-plots)
- [GAW Plots](#gaw-plots)
- [Steps to run generate NgVeri Model](#steps-to-run-generate-ngveri-model)
- [Steps to run this project](#steps-to-run-this-project)
- [Acknowlegdements](#acknowlegdements)
- [References](#references)
Table of contents generated with markdown-toc
## Abstract
With the increasing technology, the size of the transistors is
reducing. The reducing size leads to the tradeoff between
power, efficiency and switching time. Because of which
there is requirement to design low power transistor with less
area and lesser number of gates. The design should use
lesser power as well. Thus, making it more and more
efficient.
## Reference Circuit Diagram
## Reference Waveform
## Circuit Details
As shown in the figure we have two cross coupled
circuits of PMOS logic and NMOS logic.
On the PMOS logic we are getting the output as XOR
while in the NMOS block we get the output as XNOR.
The transistors M4 and M3 behave as a pass transistor
and pass the output of M1, M2 and M5, M6
respectively.
The advantage of the above circuit is that it uses only
6 transistors and gives both outputs of XOR and
XNOR while the general circuit uses 8 transistors with
only one output either XOR or XNOR.
This way it consumes less space and less power and is
efficient in many ways.
## Truth Table
| Input A | Input B | Output XOR | Output XNOR |
| ------------- | ------------- | ------------- | ------------- |
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1| 0|
| 1 | 0 |1|0|
| 1 | 1 |0|1|
## Software Used
### eSim
It is an Open Source EDA developed by FOSSEE, IIT Bombay. It is used for electronic circuit simulation. It is made by the combination of two software namely NgSpice and KiCAD.
For more details refer:
https://esim.fossee.in/home
### NgSpice
It is an Open Source Software for Spice Simulations. For more details refer:
http://ngspice.sourceforge.net/docs.html
### Makerchip
It is an Online Web Browser IDE for Verilog/System-verilog/TL-Verilog Simulation. Refer
https://www.makerchip.com/
### Verilator
It is a tool which converts Verilog code to C++ objects. Refer:
https://www.veripool.org/verilator/
## Circuit Diagram in eSim
The following is the schematic in eSim:
## Verilog Code
## Makerchip
```
\TLV_version 1d: tl-x.org
\SV
/* verilator lint_off UNUSED*/ /* verilator lint_off DECLFILENAME*/ /* verilator lint_off BLKSEQ*/ /* verilator lint_off WIDTH*/ /* verilator lint_off SELRANGE*/ /* verilator lint_off PINCONNECTEMPTY*/ /* verilator lint_off DEFPARAM*/ /* verilator lint_off IMPLICIT*/ /* verilator lint_off COMBDLY*/ /* verilator lint_off SYNCASYNCNET*/ /* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNSIGNED*/ /* verilator lint_off CASEINCOMPLETE*/ /* verilator lint_off UNDRIVEN*/ /* verilator lint_off VARHIDDEN*/ /* verilator lint_off CASEX*/ /* verilator lint_off CASEOVERLAP*/ /* verilator lint_off PINMISSING*/ /* verilator lint_off BLKANDNBLK*/ /* verilator lint_off MULTIDRIVEN*/ /* verilator lint_off WIDTHCONCAT*/ /* verilator lint_off ASSIGNDLY*/ /* verilator lint_off MODDUP*/ /* verilator lint_off STMTDLY*/ /* verilator lint_off LITENDIAN*/ /* verilator lint_off INITIALDLY*/
//Your Verilog/System Verilog Code Starts Here:
module ixorxnor(output yXOR,output yXNOR, input a,input b);
assign yXOR = a ^ b;
assign yXNOR = ~(a ^ b);
endmodule
//Top Module Code Starts here:
module top(input logic clk, input logic reset, input logic [31:0] cyc_cnt, output logic passed, output logic failed);
logic yXOR;//output
logic yXNOR;//output
logic a;//input
logic b;//input
//The $random() can be replaced if user wants to assign values
always @(posedge clk)
begin
a = $random();
b = $random();
end
ixorxnor ixorxnor(.yXOR(yXOR), .yXNOR(yXNOR), .a(a), .b(b));
\TLV
//Add \TLV here if desired
\SV
endmodule
```
## Makerchip Plots
## Netlists
## NgSpice Plots
## GAW Plots
## Steps to run generate NgVeri Model
1. Open eSim
2. Run NgVeri-Makerchip
3. Add top level verilog file in Makerchip Tab
4. Click on NgVeri tab
5. Add dependency files
6. Click on Run Verilog to NgSpice Converter
7. Debug if any errors
8. Model created successfully
## Steps to run this project
1. Open a new terminal
2. Clone this project using the following command:
```git clone https://github.com/Eyantra698Sumanto/XOR-XNOR-Gate.git ```
3. Change directory:
```cd eSim_project_files/xor_xnor```
4. Run ngspice:
```ngspice xor_xnor.cir.out```
5. To run the project in eSim:
- Run eSim
- Load the project
- Open eeSchema
## Acknowlegdements
1. FOSSEE, IIT Bombay
2. Steve Hoover, Founder, Redwood EDA
3. Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - [email protected]
4. Sumanto Kar, eSim Team, FOSSEE
## References
1. Ahmad, Nabihah & Hasan, Rezaul. (2011). A new design of XOR-XNOR gates for low power application. 10.1109/ICEDSA.2011.5959039.
2. K. Ravali, N. R. Vijay, S. Jaggavarapu and R. Sakthivel, "Low power XOR gate design and its applications," 2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN), 2017, pp. 1-4, doi: 10.1109/ICSCN.2017.8085699.
3. https://github.com/Eyantra698Sumanto/Two-in-One-Low-power-XOR-XNOR-Gate.git