https://github.com/f-fathurrahman/belajarverilog
https://github.com/f-fathurrahman/belajarverilog
Last synced: 3 months ago
JSON representation
- Host: GitHub
- URL: https://github.com/f-fathurrahman/belajarverilog
- Owner: f-fathurrahman
- Created: 2017-02-13T03:20:09.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2017-03-26T01:27:26.000Z (about 8 years ago)
- Last Synced: 2025-01-13T11:49:14.032Z (5 months ago)
- Language: Verilog
- Size: 21.8 MB
- Stars: 0
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
Just simple notes about Verilog HDL which I am currently studying.