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https://github.com/fahdseddik/pipelined-processor-with-assembler
5-stage pipelined processor written in VHDL with its assembler based on a RISC ISA
https://github.com/fahdseddik/pipelined-processor-with-assembler
Last synced: about 6 hours ago
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5-stage pipelined processor written in VHDL with its assembler based on a RISC ISA
- Host: GitHub
- URL: https://github.com/fahdseddik/pipelined-processor-with-assembler
- Owner: FahdSeddik
- License: mit
- Created: 2024-04-17T17:20:14.000Z (7 months ago)
- Default Branch: main
- Last Pushed: 2024-05-18T20:28:58.000Z (6 months ago)
- Last Synced: 2024-06-22T06:59:56.664Z (5 months ago)
- Language: VHDL
- Size: 254 KB
- Stars: 1
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# 5-Stage Pipelined Processor and Assembler
This repository contains the implementation of a 5-stage pipelined processor and its corresponding assembler, designed primarily in VHDL. The design aims to mimic a real-world CPU pipeline, including components for fetching, decoding, executing, memory access, and write-back stages, along with associated hazard detection and control units.
## Instructions
First run the below commands to configure modelsim. After that, open the `Processor/Processor.mpf` file with modelsim.
```bash
$~ cd ./Processor/
$~/Processor/ python modelsim_configure.py
```
After modelsim opens you should be able to view the folder structure in the `Processor` directory duplicated in modelsim. Run the below command to ensure work library is created in the modelsim terminal
```bash
vlib work
```
## Processor Design Overview
The processor architecture is built around a 5-stage pipeline, allowing for increased instruction throughput. Each stage is designed to perform specific tasks, and files corresponding to each stage are organized within their respective directories.
## Pipeline Stages
1. *Fetch*: Responsible for fetching the next instruction from memory.
2. *Decode*: Decodes the fetched instruction and prepares necessary signals and data paths for execution.
3. *Execute*: Executes the operation specified by the instruction.
4. *Memory*: Handles data memory access, including load and store instructions.
5. *Writeback*: Completes the instruction by writing results back to registers
## Processor Components
- PC (Program Counter)
- Fetch Unit
- Decode Unit (Including various register components)
- Execute Unit (Including ALU, CCR - Condition Code Register)
- Data Memory
- Writeback Unit
- Branch Handling
- Controller Unit
- Hazard Detection Unit (HDU)
- Forwarding Unit
- Stack Pointer (SP)
## Folder Structure
```
├── Processor/
│ ├── Fetch/
│ │ ├── PC.vhd (Program Counter)
│ │ ├── Fetch.vhd
│ │ └── ...
│ ├── Decode/
│ │ ├── Decode.vhd
│ │ ├── Decode0Registers.vhd
│ │ ├── Decode1Registers.vhd
│ │ ├── Decode2Registers.vhd
│ │ ├── Decode3Registers.vhd
│ │ ├── RegisterFile.vhd
│ │ ├── ControllerUnit.vhd
│ │ └── ...
│ ├── Execute/
│ │ ├── Execute.vhd
│ │ ├── CCR.vhd (Condition Code Register)
│ │ ├── ALU.vhd (Arithmetic Logic Unit)
│ │ └── ...
│ ├── Memory/
│ │ ├── DataMemory.vhd
│ │ ├── SP.vhd (Stack Pointer)
│ │ └── ...
│ ├── Writeback/
│ │ ├── Writeback.vhd
│ │ └── ...
│ ├── HazardDetection/
│ │ ├── HDU.vhd (Hazard Detection Unit)
│ │ ├── BranchPrediction.vhd
│ │ └── ForwardingUnit.vhd
│ ├── General/
│ │ ├── Register.vhd
│ │ └── ... (rest of tiny components)
├── Assembler/
│ ├── assembler.py
│ └── example.txt
└── Diagrams/
├── ...
└── ... (rest of deliverables)
```
# Assembler
Included is a Python-based assembler (`assembler.py`) that translates assembly code into machine code understood by the processor. An example assembly file (`example.txt`) is also provided to demonstrate usage.