https://github.com/faisalahmedbijoy/sap-1-computer-design-logisim

Simple As Possible (SAP) 1 Computer Design in Logisim
https://github.com/faisalahmedbijoy/sap-1-computer-design-logisim

alu hardware-designs logisim sap system-programming

Last synced: 7 months ago
JSON representation

Simple As Possible (SAP) 1 Computer Design in Logisim

• Host: GitHub
• URL: https://github.com/faisalahmedbijoy/sap-1-computer-design-logisim
• Owner: FaisalAhmedBijoy
• Created: 2021-06-09T17:31:18.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2021-06-29T05:37:56.000Z (over 4 years ago)
• Last Synced: 2025-01-19T16:38:14.363Z (9 months ago)
• Topics: alu, hardware-designs, logisim, sap, system-programming
• Homepage:
• Size: 2.54 MB
• Stars: 12
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
# SAP-1-Computer-Design-Logisim

Simple As Possible (SAP) 1 Computer Design in Logisim

My Youtube Tutorial Link: https://youtu.be/XYyqAYkaPH4 


SAP1 Computer Functionalities


- Program Counter

- Input and MAR

- RAM

- Instruction Register

- Controller

- Accumulator (A)

- Adder and Subtractor

- B Register

- Output Register

- Binary Display

Main Circuit


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/sap1%202.PNG)

Full Adder


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(353).png)

Register 4 bit 


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(354).png)

Register 8 bit


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(355).png)

Arithmetic Logic Unit (ALU)


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(356).png)

Program Counter: Ripple Counter


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(357).png)

Ring Counter


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(358).png)

Instruction Decoder


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(359).png)

Controller / Sequencer


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(360).png)

Main Circuit


![alt text](https://github.com/FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim/blob/main/imageReadMeSap1/Screenshot%20(361).png)