https://github.com/farlepet/subleq_verilog
Basic implementation of a SUBLEQ CPU in Verilog
https://github.com/farlepet/subleq_verilog
Last synced: 3 months ago
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Basic implementation of a SUBLEQ CPU in Verilog
- Host: GitHub
- URL: https://github.com/farlepet/subleq_verilog
- Owner: farlepet
- Created: 2020-10-03T04:15:11.000Z (over 4 years ago)
- Default Branch: master
- Last Pushed: 2020-10-03T04:15:46.000Z (over 4 years ago)
- Last Synced: 2025-01-11T22:20:38.424Z (4 months ago)
- Language: Verilog
- Size: 10.7 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0