https://github.com/ferasaljoudi/classesschedule

A classes schedule designed on BASYS3 (FPGA) using VHDL and Vivado
https://github.com/ferasaljoudi/classesschedule

Last synced: 7 days ago
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A classes schedule designed on BASYS3 (FPGA) using VHDL and Vivado

• Host: GitHub
• URL: https://github.com/ferasaljoudi/classesschedule
• Owner: ferasaljoudi
• License: mit
• Created: 2023-11-21T19:46:35.000Z (12 months ago)
• Default Branch: main
• Last Pushed: 2024-07-05T15:31:39.000Z (5 months ago)
• Last Synced: 2024-07-05T20:41:11.887Z (5 months ago)
• Language: VHDL
• Size: 3.22 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.md
  • Security: SECURITY.md

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README

        


    






This is an individual lab project for the ENEL384 class. The requirement of the project is to design a synchronous circuit of reasonable complexity ( > 1 stage, < 100 stages), which means that the project can not be composed solely of combinational logic.

To design the chosen project (Class Schedules), I used VHSIC Hardware Description Language (VHDL), Vivado (a software for hardware description language designs) and the BASYS-3 FPGA 

Board.






    








    

    

    








    








  

    

        

        


        

        


        

    

  








    






In the FPGA board, I used:

- Four Switches to turn ON or OFF the 4 classes/subjects.

- Five buttons to select what do we want to display

    - Left button for class

    - Center button for lab

    - Right button for seminar

    - Top button for midterm

    - Bottom button for final

- Four 7-Segments to display class names, time and date.

- The first 4 LEDs on the right of the FPGA to highlight which switch is corresponding to which class

- The first 5 LEDs on the left of the FPGA to represent the weekdays (Monday to Friday)

To display 4 different letters/numbers on the four 7-segment displays where the anode of each 7- segment is driven from four transistors which have common 3.3V, I used a multiplexing technique. I created a clock which will switch between each display at intervals of 0.0025 seconds, which is too fast for the human eye to discern. I produce the illusion that all four displays are lighting simultaneously. This allowed me to represent different letters/numbers on each display.

Then I created a second clock which is for 3 seconds. When all 4 switches are OFF, this clock allows me to represent the pattern of the 4 LEDs on the right of the FPGA. Each LED is represented for 3 seconds and it highlights a class switch. Along with these LEDs, the 7 segment displays the name of the class for the corresponding led, and the 5 LEDs on the left will display the days that are occupied by the displayed class.

Then I used combinational logic (if, elsif, case) to determine the output (9 LEDs and 7 segment display) based on the input (4 switches and 5 buttons).






    






To view the YouTube video demonstrating the ClassesSchedule on the FPGA:

- _Click Here_

### Note:

I only had to write the Enel384Project.vhd file. The Basys-3-Master.xdc is a general .xdc file for the Basys3, and it is essential to define the pins and constraints for the Basys3 FPGA board. To view the .xdc file on the Digilent website:

Click _HERE_ then find the "Master XDC Files" link.