https://github.com/fpgawars/icepll
PLL collection for IceStudio
https://github.com/fpgawars/icepll
fpga fpgawars icestudio pll
Last synced: 2 months ago
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PLL collection for IceStudio
- Host: GitHub
- URL: https://github.com/fpgawars/icepll
- Owner: FPGAwars
- License: gpl-3.0
- Created: 2021-12-07T08:23:02.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2025-02-04T06:41:23.000Z (4 months ago)
- Last Synced: 2025-03-22T16:52:51.976Z (3 months ago)
- Topics: fpga, fpgawars, icestudio, pll
- Language: JavaScript
- Homepage: https://github.com/FPGAwars/icePLL/wiki
- Size: 154 KB
- Stars: 2
- Watchers: 6
- Forks: 2
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# icepll Collection
[![Icestudio][icestudio-image]][icestudio-url]
![Version][version-image]
Working with PLLs (Phase Locked Loops)
## Documentation
Find all the information on the [WIKI page](https://github.com/FPGAwars/icePLL/wiki)
## License
Licensed under [LGPL-3.0](https://opensource.org/licenses/LGPL-3.0).
## Install
For installing and using this collection in Icestudio follow these steps:
* Download the collection: [stable](https://github.com/FPGAwars/icePLL/archive/refs/tags/v0.1.0.zip) or [development](https://github.com/FPGAwars/icePLL/archive/refs/heads/main.zip)
* Install the collection: *Tools > Collections > Add*
* Select the collection: *Select > Collection*
## Usage for ice40 chip series
In the collection manager the icePLL-main menu should now be visible. Here you can find PLL blocks for the ice40 and ECP5 chips.
For the ice40 LP/HX the PLL's are located at I/O bank 2, see the ice40 [datasheet](https://datasheet.lcsc.com/lcsc/2201180600_Lattice-ICE40HX4K-TQ144_C1521989.pdf) under "Architecture Overview.
For other chipset checkout their datasheet's, fx via octopart.
The PLL's can use a reference clk directly, if the clk is connected to an GBIN on I/O bank 2, in the case of the ice40 LP/HX series. Otherwise the reference clk can be used in-directly.
This results in longer routing, leading to a potionel issue at higher freqencies although not yet confirmed.
If a clk is connected directly to the PLL's, then the pll40_pad should be used. If clk is not directly connected then pll40_core.
## Usage for ECP5
* TODO
## Authors
* [Carlos Venegas](https://github.com/cavearr)
## Contributors
* [Obijuan](https://github.com/Obijuan)
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[icestudio-image]: https://img.shields.io/badge/collection-icestudio-blue.svg
[icestudio-url]: https://github.com/FPGAwars/icestudio
[version-image]: https://img.shields.io/badge/version-v0.1.0-orange.svg