https://github.com/gcerpa01/compe470
Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023
https://github.com/gcerpa01/compe470
verilog verilog-hdl vivado
Last synced: 8 months ago
JSON representation
Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023
- Host: GitHub
- URL: https://github.com/gcerpa01/compe470
- Owner: Gcerpa01
- Created: 2023-04-24T03:53:00.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-04-24T04:04:17.000Z (over 2 years ago)
- Last Synced: 2025-01-17T00:42:04.788Z (10 months ago)
- Topics: verilog, verilog-hdl, vivado
- Language: Verilog
- Homepage:
- Size: 7.5 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files: