https://github.com/geekalexis/superscalar-mips

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
https://github.com/geekalexis/superscalar-mips

mips processor-architecture verilog

Last synced: 3 months ago
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A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

• Host: GitHub
• URL: https://github.com/geekalexis/superscalar-mips
• Owner: GeekAlexis
• Created: 2019-04-12T03:14:54.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2019-11-28T23:41:29.000Z (over 6 years ago)
• Last Synced: 2025-03-02T04:44:05.464Z (over 1 year ago)
• Topics: mips, processor-architecture, verilog
• Language: Verilog
• Homepage:
• Size: 47.1 MB
• Stars: 10
• Watchers: 2
• Forks: 3
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Superscalar-MIPS