https://github.com/geekdude/axi4-stream-clock-converter
https://github.com/geekdude/axi4-stream-clock-converter
Last synced: 4 months ago
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- Host: GitHub
- URL: https://github.com/geekdude/axi4-stream-clock-converter
- Owner: Geekdude
- License: mit
- Created: 2020-04-08T15:54:17.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2021-01-30T21:40:34.000Z (almost 5 years ago)
- Last Synced: 2025-07-13T03:47:20.185Z (5 months ago)
- Language: VHDL
- Size: 227 KB
- Stars: 4
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# AXI4-Stream Clock Converter
Designed by Aaron Young
This repository contains a custom AXI4-Stream clock converter design I created using VHDL for my PhD dissertation to convert an [AXI4-Stream](https://static.docs.arm.com/ihi0051/a/IHI0051A_amba4_axi4_stream_v1_0_protocol_spec.pdf) from one clock domain to another clock domain using a bi-directional toggle synchronizer design. A detailed description of the design can be found in my dissertaion, [SNACC: The Scaled-up Neuromorphic Array Communications Controller](https://trace.tennessee.edu/utk_graddiss/5843/), in Section 7.3.2 starting on page 146. This clock convert is designed to have minimal latency and was shown to have less latency than the AXI4-Stream components included with Vivado.
## Citing
If you use this repository, please cite my dissertation [SNACC: The Scaled-up Neuromorphic Array Communications Controller](https://trace.tennessee.edu/utk_graddiss/5843/).
### Recommended Citation
Plain Text:
Young, Aaron Reed, "SNACC: The Scaled-up Neuromorphic Array Communications Controller. " PhD diss., University of Tennessee, 2020.
https://trace.tennessee.edu/utk_graddiss/5843
Bibtex:
@PhdThesis{young_snacc,
author = {Aaron Reed Young},
title = {SNACC: The Scaled-up Neuromorphic Array Communications Controller},
date = {2020},
institution = {University of Tennessee},
}
## Usage
The AXI4-Stream clock converter converts an AXI4-Stream from one clock domain to another clock domain. The clock converter can work with any width of data and the `DATA_WIDTH` generic is use to specify the width of the tdata bus.
Component Declaration:
```vhdl
COMPONENT axis_clock_converter
GENERIC (
DATA_WIDTH : positive := 512
);
PORT (
areset_n : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
m_axis_aclk : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
```
Component Instantiation:
```vhdl
clock_converter : axis_clock_converter
GENERIC MAP (
DATA_WIDTH => 512
)
PORT MAP (
areset_n => areset_n,
s_axis_aclk => s_axis_aclk,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
m_axis_aclk => m_axis_aclk,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata
);
```
## Testbench
A testbench for the AXI4-Steam clock converter can be found in the `testbench` folder. The testbench was originally used with [Xilinx Vivado](https://www.xilinx.com/products/design-tools/vivado.html), but it can also be ran with the open-source [GHDL](http://ghdl.free.fr/) simulator. A generic [Python 3](https://www.python.org/) script is provided in `scripts/` to make running testbenches with GHDL easier. With testbench can be ran with
```bash
python3 scripts/run_testbenches.py -t testbench/axis_clock_converter_tb.vhd
```