Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/gmbeddard/ee201-funds-comp-engineering-risc5cpuproject
A step-by-step implementation of a RISC-V CPU using SystemVerilog, including modules for ALU operations, memory instructions, and branching. Features testbenches, assembler integration, and optional FPGA deployment for real-world testing. Perfect for exploring CPU architecture and hardware design.
https://github.com/gmbeddard/ee201-funds-comp-engineering-risc5cpuproject
assembly-language computer-engineering cpu risc-v systemverilog
Last synced: 4 days ago
JSON representation
A step-by-step implementation of a RISC-V CPU using SystemVerilog, including modules for ALU operations, memory instructions, and branching. Features testbenches, assembler integration, and optional FPGA deployment for real-world testing. Perfect for exploring CPU architecture and hardware design.
- Host: GitHub
- URL: https://github.com/gmbeddard/ee201-funds-comp-engineering-risc5cpuproject
- Owner: gmbeddard
- Created: 2025-01-12T01:21:09.000Z (5 days ago)
- Default Branch: main
- Last Pushed: 2025-01-12T01:27:56.000Z (5 days ago)
- Last Synced: 2025-01-12T02:30:34.780Z (5 days ago)
- Topics: assembly-language, computer-engineering, cpu, risc-v, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 94.7 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0