https://github.com/godtamit/tomasulo-simulation
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
https://github.com/godtamit/tomasulo-simulation
hardware processor processor-architecture processor-simulator simulation tomasulo
Last synced: 3 months ago
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A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
- Host: GitHub
- URL: https://github.com/godtamit/tomasulo-simulation
- Owner: GodTamIt
- Created: 2017-04-22T21:35:55.000Z (almost 9 years ago)
- Default Branch: master
- Last Pushed: 2017-04-22T21:50:42.000Z (almost 9 years ago)
- Last Synced: 2025-04-15T23:36:46.217Z (10 months ago)
- Topics: hardware, processor, processor-architecture, processor-simulator, simulation, tomasulo
- Language: C++
- Size: 364 KB
- Stars: 14
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Tomasulo Simulation
## Introduction
This project is an educational simulation of the [Tomasulo algorithm](https://en.wikipedia.org/wiki/Tomasulo_algorithm), a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
## Implementation
Below are some of the key concepts of the simulation's algorithm:
* **Reorder Buffer:** simulates branching resolution using a reorder buffer
* **Register Renaming:** a technique to minimize data hazards
* **Result Buses:** unlike the original Tomasulo algorithm, which contains a single *Common Data Bus (CDB)*, there can be multiple result buses to update the state of the pipeline.
* **Reservation Station Scheduling:** units of scheduling managing an instruction fired to a *Function Unit*
* **Specialized Function Units:** specialized hardware units specific to different types of instructions
* **Gselect Branch Prediction:** a global branch prediction scheme that keeps a pattern history table and concatenates the global branch history