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https://github.com/gousaiyang/se345-digital-design

Projects of SE345 course (Digital Logic Design of Computer Components).
https://github.com/gousaiyang/se345-digital-design

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Projects of SE345 course (Digital Logic Design of Computer Components).

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# SE345-digital-design

## Introduction

This is a repo which contains projects of the course **Digital Logic Design of Computer Components** (SE345) in SJTU in year 2017-2018.

## Contents

- `my_first_fpga`: A demo project provided by Altera to help you get familiar with FPGA/verilog designing process.
- `stopwatch`: A stopwatch. For more details see [experiment report](./stopwatch/stopwatch_report.pdf).
- `sc_computer`: A single-cycle CPU. A [truth table](./sc_computer/Truth_Table_to_student.xlsx) is provided and fulfilled. For more details see [experiment report](./sc_computer/sc_computer_report.pdf).
- `pipe_computer`: A pipelined CPU. For more details see [experiment report](./pipe_computer/pipe_computer_report.pdf).
- `exp_exam`: Solution to the experiment exam. For more details see [here](../../tree/master/exp_exam).
- `number_game`: A number game based on the FPGA board. This is a freely-chosen extension project. For more details see [experiment report](./number_game/number_game_report.pdf).
- An [experiment manual](./软件学院2015级数字部件设计课程实验指导书_v0.8.pdf) provided by our instructor.

## License

- Usage of the project `my_first_fpga`, and Altera-generated files in other projects, should follow Altera's license.
- Projects `sc_computer`, `pipe_computer`, `exp_exam` and the experiment manual contain materials provided by instructors/textbook authors/TAs/former students. They should only be used for educational purposes.
- Other code completed by myself follows the MIT License.