https://github.com/govindjeevan/weighted-round-robin-arbiter

Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
https://github.com/govindjeevan/weighted-round-robin-arbiter

Last synced: 4 months ago
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Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components

• Host: GitHub
• URL: https://github.com/govindjeevan/weighted-round-robin-arbiter
• Owner: govindjeevan
• Created: 2018-03-10T11:02:20.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2018-03-10T11:26:43.000Z (over 8 years ago)
• Last Synced: 2025-08-06T13:48:11.674Z (10 months ago)
• Language: Verilog
• Homepage:
• Size: 418 KB
• Stars: 19
• Watchers: 0
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Weighted-Round-Robin-Arbiter

Mini-Project: CO202 - Design Of Digital Systems

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Reg:       	

GOVIND JEEVAN       16CO221

BIDYADHAR MOHANTY   16CO212

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Instructions Specific to each are given in the corresponding folders.

![alt text](https://image.ibb.co/hvr2iS/Screenshot_from_2018_03_10_16_39_41.png)