https://github.com/gracesevillano/rtic-project-antoine-s-army

This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed
https://github.com/gracesevillano/rtic-project-antoine-s-army

fpga-programming nexys4ddr vhdl-code

Last synced: about 2 months ago
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This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed

• Host: GitHub
• URL: https://github.com/gracesevillano/rtic-project-antoine-s-army
• Owner: GraceSevillano
• Created: 2023-12-22T16:40:32.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-01-02T13:47:18.000Z (over 1 year ago)
• Last Synced: 2025-01-12T02:43:47.577Z (3 months ago)
• Topics: fpga-programming, nexys4ddr, vhdl-code
• Language: VHDL
• Homepage:
• Size: 12.3 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Basic FPGA Microprocessor on Nexys4DDR - Project 

## Project Overview

This project involves creating a basic microprocessor on an FPGA platform, specifically the Nexys4DDR board.



    



### Components

- **cpu_top.vhd**: Top-level entity integrating the CPU, RAM, and display modules.

- **cpu.vhd**: CPU core executing instructions.

- **disp4.vhd**: Manages the Nexys4DDR board's 7-segment display.

- **procram.vhd**: Simulates RAM for data storage and retrieval.

![Schematic Diagram](images/schematic_first_second_implementation.png)

### Functionality

Executes basic operations like load, store, add, and jump based on opcodes.

### Clocks

Uses a debounced clock for inputs and a divided clock for display operations.

## Implementation Steps

1. **Environment Setup**: Initialize your FPGA development environment.

2. **Configure Constraints**: Apply `.xdc` constraints for the Nexys4DDR board.

3. **Synthesis**: Compile VHDL files and synthesize the design.

4. **Simulation**: Use testbench to verify functionality.

5. **Board Programming**: Load the bitstream onto the Nexys4DDR.

6. **Operation**: Observe instruction execution on the 7-segment display.

## Files Explanation

Each VHDL file contains comments for a better understanding of the system.

 

Details are in our report RTIC_project.pdf