https://github.com/grebe/ofdm

Chisel Things for OFDM
https://github.com/grebe/ofdm

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 10 days ago
JSON representation

Chisel Things for OFDM

• Host: GitHub
• URL: https://github.com/grebe/ofdm
• Owner: grebe
• License: bsd-3-clause
• Created: 2018-01-19T21:11:20.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2020-07-01T03:11:14.000Z (over 4 years ago)
• Last Synced: 2024-10-10T20:45:23.752Z (27 days ago)
• Topics: chip-generator, chisel, chisel3, firrtl, rtl, scala, verilog
• Language: Scala
• Size: 79.4 MB
• Stars: 30
• Watchers: 7
• Forks: 7
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# OFDM

This repository contains some blocks useful for making OFDM transceivers.

This includes:

* Autocorrelator

* CORDIC (pipelined and iterative)

* Divider

* Filters

* NCO

as well as some higher level blocks that combine these to do useful OFDM things.

`src/main/resources` contains some traces from the ADI board that are useful for testing.

## Running

To generate a synchronization block, run

```

sbt "runMain ofdm.GenerateSyncVerilog"

```

## Testing

To run a test of the synchronization block and generate a nice plot, waveforms, etc., run

```

sbt "testOnly ofdm.SyncSpec

```

The waveform will be located at `test_run_dir/ofdm.SyncSpec{RandomNumber}/Sync.vcd`.