https://github.com/gusinacio/epos-riscv
Implementation of OS epos in RiscV for INE5424
https://github.com/gusinacio/epos-riscv
cpp risc-v
Last synced: 8 months ago
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Implementation of OS epos in RiscV for INE5424
- Host: GitHub
- URL: https://github.com/gusinacio/epos-riscv
- Owner: gusinacio
- License: gpl-2.0
- Created: 2020-10-20T02:18:49.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2020-12-05T07:12:56.000Z (over 5 years ago)
- Last Synced: 2025-02-17T00:49:36.958Z (over 1 year ago)
- Topics: cpp, risc-v
- Language: C++
- Homepage:
- Size: 803 KB
- Stars: 1
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
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README
# P3 - EPOS
## Installing
Simply extract the tarball or clone the repository in a convenient location for you.
After that, it is important to check in ```makedefs``` the PATH for your compiled toolchain that targets 32-bit RISC-V.
## Testing
Go into the directory where you extracted EPOS and issue a ```make all``` to have instances of EPOS built for each of the applications in the ```app``` directory to build the intended tests for this delivery (P3).
## Running
After building an application-oriented instance of EPOS, you can run the application with the tailored EPOS on QEMU using: ```make APPLICATION= run```. The prepared tests are run with ```make APPLICATION=concurrent_philosofers_dinner run``` for atomics operations and valuation, and ```make APPLICATION=time_preemptive run``` to test the implemented scheduler in multicore. The applications run in an instance of QEMU, SiFive-E RISC-V machine.
## Tests done
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### Multicore Initialization
For the multicore initialization, all the cores start at the same entry point making a small initialization process, initializing their operation mode, the mtvec and enabling interrupts. After this initial process, all the harts except the core 0 will issue a ```wfi```, waiting for an interrupt to be waken, while the core 0 proceeds with the normal system initialization. In an opportune moment, the core 0 wakes up all the other cores issuing an IPI and all the other cores proceed with the initialization in the same way. This can be checked by the test app initialization itself, that uses 4 cores to successfully execute.
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### Atomic Operations
We implemented the ```tls```, ```finc```, ```fdec``` and ```cas``` operations in CPU using the atomic instructions in risc-v ```sc.w``` and ```lr.w```.
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### Timers configuration / Interrupt Handling
Each core has its own counter and uses offsets of 8 for every core in the mtime.
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### IPI
These are inter-processor interrupts, and can be done first enabling the interrupt id[3] and every time we write in the CLINT core offset, we create an interruption which can be used to synchronize the cores in a given point of code and create interruptions for each other.
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### Global Multicore Scheduling
The Global Multicore Scheduler implemented is a multicore version of the previously implemented Feedback Scheduling (FS). This global multicore version (GFS) is based in the Multihead Scheduling List implemented in EPOS, that represents a single scheduling list with multiple heads (one for each core), and its functioning can be seen in the test application.
It is important to note that in some executions the test may freeze, but in most cases it successfully completes.