https://github.com/gyeonghokim/riscv_core

building 32bit risc-v core and Machine Learning for Branch Prediction
https://github.com/gyeonghokim/riscv_core

fpga risc-v verilog

Last synced: about 13 hours ago
JSON representation

building 32bit risc-v core and Machine Learning for Branch Prediction

• Host: GitHub
• URL: https://github.com/gyeonghokim/riscv_core
• Owner: GyeongHoKim
• Created: 2022-05-09T05:27:21.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2023-01-29T06:15:25.000Z (almost 2 years ago)
• Last Synced: 2023-03-04T02:25:26.661Z (over 1 year ago)
• Topics: fpga, risc-v, verilog
• Language: Verilog
• Homepage:
• Size: 6.53 MB
• Stars: 0
• Watchers: 0
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# RISC-V CPU

32 bit RISC-V Core

# Overview

Our own RISC-V CPU RTL design.

![RISCVcore](./img/RISCVcore.png)

# Directories

| Name                | Contents                                            |

| ------------------- | --------------------------------------------------- |

| RISCV               | FPGA codes for actual working                       |

| algorithm           | MergeSort assembly & Instructions for this cpu      |

| testingModules      | Testing Each 5 stage pipeline modules               |

| BPML                | Machine Learning for Dynamic Branch Prediction      |

| img                 | Images for README                                   |

# References

* Computer Organization and Design RISC-V Edition The Hardware Software Interface by David A. Patterson, John L.Hennessy

* [vezzalinistefano/riscv-mergesort](https://github.com/vezzalinistefano/riscv-mergesort)

# How to simulate Each Verilog Modules

if your os is windows, then install Xilinx ISE Design Suite.

However, Xilinx is not available in Mac.

## installation for Mac

to install icarus-verilog,

``` shell

brew install icarus-verilog

```

to install gtkwave,

you just google "gtkwave" and download it anyway.

### icarus-verilog

for compile verilog files, 

``` shell

iverilog -o   

```

> you should add below codes in your testbench to make vcd files.

``` verilog

initial begin

	$dumpfile("fileName.vcd");

	$dumpvars(0,ModuleNameOfTestBench);

end

```

and then, you have to make waveform file(.vcd file).

``` shell

vvp 

```

### gtkwave

just double click on your waveform file(.vcd file) you made above.