https://github.com/haouo/vriscv-cpu
5 Stage Pipeline CPU base on RV32I with a few fiexd-length SIMD instructions support
https://github.com/haouo/vriscv-cpu
chisel riscv
Last synced: 29 days ago
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5 Stage Pipeline CPU base on RV32I with a few fiexd-length SIMD instructions support
- Host: GitHub
- URL: https://github.com/haouo/vriscv-cpu
- Owner: Haouo
- Created: 2023-03-01T17:18:55.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2023-03-01T17:21:53.000Z (about 3 years ago)
- Last Synced: 2025-12-25T14:56:41.616Z (5 months ago)
- Topics: chisel, riscv
- Language: Scala
- Homepage:
- Size: 896 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files: