https://github.com/hirbodbehnam/mips-verilog

MIPS CPU with IEEE 754 FPU implemented in Verilog. Project for computer architecture course - Spring 2022 Lectured by Dr. Hamid Sarbazi Azad
https://github.com/hirbodbehnam/mips-verilog

Last synced: 14 days ago
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MIPS CPU with IEEE 754 FPU implemented in Verilog. Project for computer architecture course - Spring 2022 Lectured by Dr. Hamid Sarbazi Azad

• Host: GitHub
• URL: https://github.com/hirbodbehnam/mips-verilog
• Owner: HirbodBehnam
• Created: 2023-09-25T11:17:24.000Z (about 1 year ago)
• Default Branch: master
• Last Pushed: 2023-09-25T11:18:45.000Z (about 1 year ago)
• Last Synced: 2024-04-24T12:56:45.874Z (7 months ago)
• Language: SystemVerilog
• Size: 1.83 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        

# Computer Architecture Project

## Project Team Kiavash

Project members:

* Hirbod Behnam: 99171333

* Hirad Davari: 99106136

* Benyamin Maleki: 99102286

* Soheil Nazari: 99102412