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https://github.com/hiyouga/digic-experiment
BUAA CST Autumn 2018 Digital Circuit Experiment
https://github.com/hiyouga/digic-experiment
digital-circuit verilog
Last synced: 17 days ago
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BUAA CST Autumn 2018 Digital Circuit Experiment
- Host: GitHub
- URL: https://github.com/hiyouga/digic-experiment
- Owner: hiyouga
- License: mit
- Created: 2018-11-13T19:47:33.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2019-11-23T09:12:04.000Z (about 5 years ago)
- Last Synced: 2024-12-22T04:28:21.873Z (about 1 month ago)
- Topics: digital-circuit, verilog
- Language: Verilog
- Homepage:
- Size: 4.01 MB
- Stars: 1
- Watchers: 3
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# digiC-experiment
BUAA CST Autumn 2018 Digital Circuit Experiment.
The documents can be found in [here](docs/).