Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/hubmartin/cyc1000_fpga_lvds_display
Display ASCII characters on dual-LVDS display with Cyclone 10 LP CYC1000 kit
https://github.com/hubmartin/cyc1000_fpga_lvds_display
Last synced: about 2 months ago
JSON representation
Display ASCII characters on dual-LVDS display with Cyclone 10 LP CYC1000 kit
- Host: GitHub
- URL: https://github.com/hubmartin/cyc1000_fpga_lvds_display
- Owner: hubmartin
- Created: 2019-11-13T15:46:42.000Z (about 5 years ago)
- Default Branch: master
- Last Pushed: 2019-11-13T16:02:49.000Z (about 5 years ago)
- Last Synced: 2024-10-28T09:35:57.659Z (3 months ago)
- Language: Verilog
- Size: 10.6 MB
- Stars: 3
- Watchers: 2
- Forks: 2
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# CYC1000_FPGA_LVDS_DISPLAY
Display ASCII characters on dual-LVDS display with Cyclone 10 LP CYC1000 kit
## Old kit with Lattice MachXO2
I interfaced the same display with older FPGA. I was just curious how the FPGA works and this was my first project. I run into all the troubles including timing constraints.
https://www.youtube.com/watch?v=MXM3ovkfT74
https://www.youtube.com/watch?v=BldAWWNUepo
## CYC1000 Arrow Trenz Kit
I wanted more powerful kit for this display so I could run some soft-core processor and also take an advantage of SDRAM which could act as a bitmap framebuffer.
## Current state
Right now the code can only display text from serial port which is saved in the BRAMs.
SDRAM seems to work but needs finalization to be used as a bitmap framebuffer. It would need burst transfers to be fast enough to keep the data flowing just in time to send them over LVDS.
