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https://github.com/hughperkins/cpu-tutorial

Tutorial on building your own CPU, in Verilog
https://github.com/hughperkins/cpu-tutorial

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Tutorial on building your own CPU, in Verilog

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# cpu-tutorial

Exercises to guide you through building your own CPU, from scratch, in verilog

## pre-requisites

- you should already have a grounding in verilog
- one way to do this is to work your way through the questions at https://hdlbits.01xz.net/wiki/Main_Page
- I didn't finish these, but I did many of them; you can see the ones I did personally at https://hdlbits.01xz.net/wiki/Special:VlgStats/3D7115FE8A440C29
- note: I'm not affiliated, I just found it was quite useful for me
- make sure you complete the `game of life` problem, since you are going to be building tons of finite state machines, and this problem is good practice
- to learn verilog, hdlbits isn't enough: this just provides short-term validation, practice, and dopamine-stimulation that you are in fact learning
- one resource that is quite useful for learning is https://www.doulos.com/knowhow/verilog/ (note: I'm not affiliated, I just found it worked well for me)
- you can google around the web for other resources as you go
- you'll need to install some simulators and synthesizers. I use:
- [iverilog](http://iverilog.icarus.com/)
- [verilator](https://www.veripool.org/verilator/)
- [yosys](https://github.com/YosysHQ/yosys)
- you'll need a text editor, or development environment. I use the following:
- [Visual Studio Code](https://code.visualstudio.com/)
- know at least one programming language you can use to write host-side code, such as assemblers
- python or C++ are both ok. I used python initially

Note that *all* the above resources can be used without needing to buy licenses or similar.

## Exercises

- [exercises.md](/exercises.md)