https://github.com/hukenovs/adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
https://github.com/hukenovs/adc_configurator

adc adc-configurator altera analog-signals cic dac ddc ddr dds digital-signal-processing dsp fir jesd204b serdes-mode serial-interface vhdl xilinx

Last synced: 7 months ago
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ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

• Host: GitHub
• URL: https://github.com/hukenovs/adc_configurator
• Owner: hukenovs
• License: mit
• Created: 2016-10-26T19:21:56.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2018-08-29T09:42:43.000Z (about 7 years ago)
• Last Synced: 2025-01-20T13:44:27.810Z (9 months ago)
• Topics: adc, adc-configurator, altera, analog-signals, cic, dac, ddc, ddr, dds, digital-signal-processing, dsp, fir, jesd204b, serdes-mode, serial-interface, vhdl, xilinx
• Language: VHDL
• Size: 17.6 KB
• Stars: 12
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)