https://github.com/hxlnt/8bw-verilog-samples

Verilog sample code for use with the 8-bit Workshop IDE
https://github.com/hxlnt/8bw-verilog-samples

Last synced: 26 days ago
JSON representation

Verilog sample code for use with the 8-bit Workshop IDE

• Host: GitHub
• URL: https://github.com/hxlnt/8bw-verilog-samples
• Owner: hxlnt
• Created: 2019-03-14T12:51:32.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2019-03-14T12:51:56.000Z (almost 6 years ago)
• Last Synced: 2024-10-28T05:01:03.470Z (2 months ago)
• Size: 0 Bytes
• Stars: 2
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# 8bw-verilog-samples

My Verilog sample code for use with the [8-bit Workshop IDE](8bitworkshop.com/v3.3.0/?platform=verilog). For now, most are simply annotated rewrites of the included samples.