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https://github.com/hxlnt/altera-de1-samples
Verilog code samples for Altera DE1 FPGA
https://github.com/hxlnt/altera-de1-samples
Last synced: 27 days ago
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Verilog code samples for Altera DE1 FPGA
- Host: GitHub
- URL: https://github.com/hxlnt/altera-de1-samples
- Owner: hxlnt
- License: mit
- Created: 2019-03-28T15:46:44.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2019-03-28T15:46:46.000Z (almost 6 years ago)
- Last Synced: 2024-10-28T05:01:03.399Z (2 months ago)
- Size: 1000 Bytes
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# altera-de1-samples
Verilog code samples for Altera DE1 FPGA