https://github.com/i3abghany/aes
Low-power, low-area AES encryption core.
https://github.com/i3abghany/aes
aes aes-encryption fpga vhdl
Last synced: about 1 month ago
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Low-power, low-area AES encryption core.
- Host: GitHub
- URL: https://github.com/i3abghany/aes
- Owner: i3abghany
- Created: 2020-10-23T00:01:08.000Z (almost 5 years ago)
- Default Branch: master
- Last Pushed: 2021-01-14T07:26:41.000Z (over 4 years ago)
- Last Synced: 2025-03-26T18:34:01.651Z (7 months ago)
- Topics: aes, aes-encryption, fpga, vhdl
- Language: VHDL
- Homepage:
- Size: 142 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# AES
Implementation of the AES encryption on the software using C++ and a hardware implementation using VHDL.
For the VHDL design, The overall resources consumption, using Xilinx Vivado's Synthesizer for a Zynq board:
• 1433 SLice LUTs. (0.47%)
• Slice FFs: 384. (0.06%)
Achieved maximum frequency of 225 MHz.
Achieved (comparatively) low-area design using one stage that represents a round as a feedback loop, hence utilizing less SBoxes and therefore better area utilization.
Previous design contained ten-stage pipelined datapath that could process blocks in a pipelined fashion, but was approximately six times larger area-wise because each round had its own SBoxes.
Implemented fully parallel KeyExpansion step as described in the following paper: https://eprint.iacr.org/2016/789.pdf
MixColumns step is also accelerated using bitwise operations to carry out arithmetic over the Galois Field instead of precomuting and using a lookup table, which would be much slower and much more area-hogging.