https://github.com/icarogabryel/flote
Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.
https://github.com/icarogabryel/flote
computer-architecture computer-organization digital-circuits eletronics framework hardware-description-language hardware-designs hdl integrated-circuits processor-architecture python python-module simulation
Last synced: 3 months ago
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Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.
- Host: GitHub
- URL: https://github.com/icarogabryel/flote
- Owner: icarogabryel
- License: gpl-3.0
- Created: 2024-10-19T19:50:53.000Z (8 months ago)
- Default Branch: main
- Last Pushed: 2025-03-19T15:21:14.000Z (3 months ago)
- Last Synced: 2025-03-19T16:24:10.215Z (3 months ago)
- Topics: computer-architecture, computer-organization, digital-circuits, eletronics, framework, hardware-description-language, hardware-designs, hdl, integrated-circuits, processor-architecture, python, python-module, simulation
- Language: Python
- Homepage:
- Size: 172 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE.md
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README
# Flote
## Introduction
Flote is a hardware description language and Python framework for simulation. It is designed to be **friendly, simple, light and productive**. More easy to use and learn than Verilog and VHDL. Using Flote, you can create integrated circuits component by using it's HDL and/or Python framework that work by the HLS (High Level Synthesis) concept.
## Release
Flooat is in development and is not ready for production. The beta version is expected to be released in april.
## Example
Here is an example of a half adder in Flote:
```flote
comp halfAdder {
in bit a;
in bit b;
out bit sum = a xor b;
out bit carry = a and b;
}
```
## How it works
Flote's Evaluator uses a structure of a compiler's front-end to elaborate the component. It has a scanner, parser and a builder. This last one is responsible for build the component, an object that can be manipulated in Python and simulates the behavior of the integrated circuit. The model object it's a set of signals buses and uses event driven algorithm and dynamic programming to simulate the behavior of the circuit.
Using the HLS side, you can create the component by hand. Also with the use of the Python package you can manipulate the signals and sava then in a waveform file.
## To Do List
- [X] Make the simulator class
- [X] Make EBNF for the language
- [X] Make Scanner
- [X] Make Parser
- [X] Make Builder
- [X] Make accept expressions
- [X] Improve the algorithm of simulation
- [X] Improve structure
- [X] Improve declaration and assignment
- [X] Improve Semantic Analysis
- [ ] Create waveform class
- [ ] Add line number in semantic errors
- [ ] Add multi-bit signals support
- [ ] Add multi-bit signals addressing support
- [ ] Add sub-components support
- [ ] Add Python calls support
- [ ] Improve HLS support
- [ ] Add manual time control
- [ ] Add others file types support for waveforms