https://github.com/ieee-nitk/risc-v-soc

SoC project
https://github.com/ieee-nitk/risc-v-soc

Last synced: 4 days ago
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SoC project

• Host: GitHub
• URL: https://github.com/ieee-nitk/risc-v-soc
• Owner: IEEE-NITK
• Created: 2023-01-24T09:59:57.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2023-04-03T11:13:36.000Z (over 1 year ago)
• Last Synced: 2024-12-04T05:26:48.906Z (28 days ago)
• Language: Verilog
• Homepage:
• Size: 6.18 MB
• Stars: 1
• Watchers: 6
• Forks: 2
• Open Issues: 2

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