https://github.com/iehgit/misciv
16-bit MISC processor for FPGA with specialized registers, VGA/UART/audio I/O, dual interrupts, and Altair-style front panel programming mode
https://github.com/iehgit/misciv
Last synced: 4 months ago
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16-bit MISC processor for FPGA with specialized registers, VGA/UART/audio I/O, dual interrupts, and Altair-style front panel programming mode
- Host: GitHub
- URL: https://github.com/iehgit/misciv
- Owner: iehgit
- Created: 2025-08-17T11:01:38.000Z (10 months ago)
- Default Branch: master
- Last Pushed: 2025-08-24T15:37:25.000Z (10 months ago)
- Last Synced: 2025-08-24T18:42:36.276Z (10 months ago)
- Language: SystemVerilog
- Size: 113 KB
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 0