https://github.com/ilyachichkov/risc_v-cpu
Educational project which goal is realization of processor with RISC-V architecture.
https://github.com/ilyachichkov/risc_v-cpu
hardware risc-v system-verilog
Last synced: 4 months ago
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Educational project which goal is realization of processor with RISC-V architecture.
- Host: GitHub
- URL: https://github.com/ilyachichkov/risc_v-cpu
- Owner: IlyaChichkov
- Created: 2022-12-13T21:34:23.000Z (over 2 years ago)
- Default Branch: master
- Last Pushed: 2022-12-14T19:09:19.000Z (over 2 years ago)
- Last Synced: 2025-01-04T21:27:45.047Z (5 months ago)
- Topics: hardware, risc-v, system-verilog
- Language: SystemVerilog
- Homepage:
- Size: 282 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# RISC-V | PROCESSOR
## Overview
- [Description](#description)
- [Scheme](#scheme)
- [Progress](#progress)
- [What I learned](#what-i-learned)
- [Useful resources](#useful-resources)
- [Software](#software)
- [Author](#author)
## Description
The centric point of this project is the development of the main components of the CPU with RISC-V architecture, memory, and controlling peripheral devices. The processor includes an instructions decoder, register memory, interrupt controller, arithmetic logic unit (ALU), and load-save unit (LSU). You can learn the main connection principles and components from the scheme below.
### Scheme
## Progress
### What I learned
First of all, I got a basic understanding of how CPU works and took part in it's development. The simulationg of machinary processes in real time while code was growing with feartures and turning more complicated was awesome. The whole work consists of SystemVerilog, and Verilog code, so I improved my skills in these languages.
Learning was separeted on eight parts:
- ALU
- Register File & Memory
- Decoder
- Datapath
- Load/Store Unit
- Interrupt Subsystem
- Peripheral Units
- C Programming
### Useful resources
- [RISC-V instructions simulator](https://venus.kvakil.me/) - [Github](https://github.com/kvakil/venus)
- [RISC-V specification](https://riscv.org/technical/specifications/)
### Software
__List of used software:__
* Vivado 2020.1
* Visual Studio Code
* Git
### Author
- [Ilya Chichkov](https://github.com/IlyaChichkov)