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https://github.com/ilyachichkov/risc_v-cpu
Educational project which goal is realization of processor with RISC-V architecture.
https://github.com/ilyachichkov/risc_v-cpu
hardware risc-v system-verilog
Last synced: 7 days ago
JSON representation
Educational project which goal is realization of processor with RISC-V architecture.
- Host: GitHub
- URL: https://github.com/ilyachichkov/risc_v-cpu
- Owner: IlyaChichkov
- Created: 2022-12-13T21:34:23.000Z (almost 2 years ago)
- Default Branch: master
- Last Pushed: 2022-12-14T19:09:19.000Z (almost 2 years ago)
- Last Synced: 2023-05-05T14:26:22.162Z (over 1 year ago)
- Topics: hardware, risc-v, system-verilog
- Language: SystemVerilog
- Homepage:
- Size: 282 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0