https://github.com/ilyachichkov/verilog_labs_2023

Verilog & C Language practice
https://github.com/ilyachichkov/verilog_labs_2023

drivers fpga hardware low-level verilog

Last synced: 7 days ago
JSON representation

Verilog & C Language practice

• Host: GitHub
• URL: https://github.com/ilyachichkov/verilog_labs_2023
• Owner: IlyaChichkov
• Created: 2023-03-22T09:27:31.000Z (over 1 year ago)
• Default Branch: master
• Last Pushed: 2023-05-23T15:30:14.000Z (over 1 year ago)
• Last Synced: 2023-05-23T16:28:08.663Z (over 1 year ago)
• Topics: drivers, fpga, hardware, low-level, verilog
• Language: SystemVerilog
• Homepage:
• Size: 293 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

Awesome Lists containing this project