https://github.com/inhald/asip_stepper_motor_control

8-bit RISC ASIP for Stepper Motor Controller with both full and half step capabilities. Implemented in Verilog HDL.
https://github.com/inhald/asip_stepper_motor_control

asip risc-v stepper-motor-control verilog-hdl

Last synced: 3 months ago
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8-bit RISC ASIP for Stepper Motor Controller with both full and half step capabilities. Implemented in Verilog HDL.

• Host: GitHub
• URL: https://github.com/inhald/asip_stepper_motor_control
• Owner: inhald
• License: mit
• Created: 2025-04-07T01:03:41.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2025-04-07T01:55:33.000Z (6 months ago)
• Last Synced: 2025-06-06T01:26:26.151Z (4 months ago)
• Topics: asip, risc-v, stepper-motor-control, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 10 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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