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https://github.com/intel/rohd-hcl
A hardware component library developed with ROHD.
https://github.com/intel/rohd-hcl
component-library hardware hardware-components hardware-design reusable-components rohd systemverilog
Last synced: about 2 months ago
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A hardware component library developed with ROHD.
- Host: GitHub
- URL: https://github.com/intel/rohd-hcl
- Owner: intel
- License: bsd-3-clause
- Created: 2023-03-30T20:43:35.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2024-11-15T20:26:09.000Z (about 2 months ago)
- Last Synced: 2024-11-15T20:34:14.225Z (about 2 months ago)
- Topics: component-library, hardware, hardware-components, hardware-design, reusable-components, rohd, systemverilog
- Language: Dart
- Homepage: https://pub.dev/packages/rohd_hcl
- Size: 23.9 MB
- Stars: 81
- Watchers: 5
- Forks: 23
- Open Issues: 31
-
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
- Code of conduct: CODE_OF_CONDUCT.md
- Security: SECURITY.md
Awesome Lists containing this project
- awesome-opensource-hardware - rohd-hcl
README
[](https://github.com/codespaces/new?hide_repo_select=true&ref=main&repo=621521356)
[](https://intel.github.io/rohd-hcl/confapp/)
[](https://github.com/intel/rohd-hcl/actions/workflows/general.yml)
[](https://intel.github.io/rohd-hcl/rohd_hcl/rohd_hcl-library.html)
[](https://discord.gg/jubxF84yGw)
[](https://github.com/intel/rohd-hcl/blob/main/LICENSE)
[](https://github.com/intel/rohd-hcl/blob/main/CODE_OF_CONDUCT.md)
# ROHD Hardware Component Libary
A hardware component library developed with [ROHD](https://intel.github.io/rohd-website/). This library aims to collect a set of reusable, configurable components that can be leveraged in other designs. These components are also intended as good examples of ROHD hardware implementations.
Check out the [generator web app](https://intel.github.io/rohd-hcl/confapp/), which lets you explore some of the available components, configure them, and generate SystemVerilog.
This project is always improving and growing! In a given category, initial components are primarily focused on correctness with room for optimization from there. Please feel free to contribute or provide feedback. Check out [`CONTRIBUTING`](https://github.com/intel/rohd-hcl/blob/main/CONTRIBUTING.md) for details on how to contribute.
This project is *not* intended to be the *only* place for reusable hardware components developed in ROHD. It's not even intended to be the only *library*. Contributions are welcomed to this library, but developers are also welcome to build independent packages or libraries, even if they may overlap.
## Guidelines for Components
- All hardware components should be `Module`s so that they are convertible to SystemVerilog
- Components should be general and easily reusable
- Components should be as configurable as may be useful
- Components must be extensively tested
- Components must have excellent documentation and examples
- The first component in a category should be the simplest
- Focus on breadth of component types before depth in one type
- Add `extension`s to other classes to make component usage easier, when appropriate
## Component List
See the [component list](https://github.com/intel/rohd-hcl/blob/main/doc/README.md) for documentation on components and plans for future component development.
Some examples of component categories include:
- Encoders & Decoders
- Arbiters
- FIFOs & Queues
- Find
- Count
- Sort
- Arithmetic
- Rotate
- Counters
- Pseudorandom
- Error checking & correction
- Data flow
- Memory
- Standard interfaces
- Models
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Copyright (C) 2023-2024 Intel Corporation
SPDX-License-Identifier: BSD-3-Clause