https://github.com/itamarrocha/verilog-safe
safe made with FPGA
https://github.com/itamarrocha/verilog-safe
Last synced: 3 months ago
JSON representation
safe made with FPGA
- Host: GitHub
- URL: https://github.com/itamarrocha/verilog-safe
- Owner: ItamarRocha
- Created: 2019-09-18T19:11:20.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2019-09-18T19:17:30.000Z (over 5 years ago)
- Last Synced: 2025-01-23T10:44:04.605Z (5 months ago)
- Language: Verilog
- Size: 745 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files: