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https://github.com/itsFrank/MinecraftHDL
A Verilog synthesis flow for Minecraft redstone circuits
https://github.com/itsFrank/MinecraftHDL
Last synced: 2 days ago
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A Verilog synthesis flow for Minecraft redstone circuits
- Host: GitHub
- URL: https://github.com/itsFrank/MinecraftHDL
- Owner: itsfrank
- Created: 2016-10-05T00:44:38.000Z (about 8 years ago)
- Default Branch: master
- Last Pushed: 2020-11-25T20:09:40.000Z (almost 4 years ago)
- Last Synced: 2024-11-10T00:32:51.450Z (7 days ago)
- Language: SystemVerilog
- Homepage:
- Size: 67.3 MB
- Stars: 1,131
- Watchers: 17
- Forks: 25
- Open Issues: 10
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
- awesome-list - MinecraftHDL
README
[comment]: Images
[mux4_short]: https://github.com/itsFrank/MinecraftHDL/blob/master/screenshots/mux4_short.png?raw=true
[7seg_gif]: https://github.com/itsFrank/MinecraftHDL/blob/master/screenshots/7seg.gif?raw=true
[flow]: https://github.com/itsFrank/MinecraftHDL/blob/master/screenshots/flow.png?raw=true
# Minecraft HDL
Minecraft HDL is a digital synthesis flow for minecraft redstone circuits. It is an attempt to use industry standard design tools and methods to generate digital circuits with redstone.
### Example:
This file `multiplexer4_1.v` is a 6 input - 1 output circuit that selects one of the first 4 inputs (a, b, c, d) as the output based on the value of the last 2 inputs (x, y)
```verilog
module multiplexer4_1 ( a ,b ,c ,d ,x ,y ,dout );
output dout ;
input a, b, c, d, x, y;
assign dout = (a & (~x) & (~y)) |
(b & (~x) & (y)) |
(c & x & (~y)) |
(d & x & y);
endmodule
```
When synthesized through Minecraft HDL it produces this circuit:
![4to1mux][mux4_short]
With the 6 inputs on the right and the single output on the left
---
# Quick Links
- [Screenshots & Sample Circuits](markdown/SAMPLES.md)
- [Getting Started - Installing and Using MinecraftHDL](markdown/GETTING_STARTED.md)
- [Background Theory - Digital Design & Verilog](markdown/BACKGROUND.md)
- [How MinecraftHDL Works - Read Our Paper](markdown/minecrafthdl-digital-synthesis.pdf)
- [Developper Info - If you want to fork or contribute](markdown/DEV_SETUP.md)
- [Quick Overview - Check out our poster](https://github.com/itsFrank/MinecraftHDL/blob/master/markdown/poster_pdf.pdf)
---
# About
![MHDL_FLOW][flow]
MinecraftHDL was the final undergraduate design project made by three students in the Electrical, Computer & Software Engineering department at McGill University.
It is by no means bug-free or even complete; It produces objectively inferior circuits to 'hand-made' redstone designs, and is not intended to be used in modded survival. It can generate almost any verilog circuit, however only simple designs will actually be testable in-game since any moderately-complex design will end up being longer than the maximum number of blocks loaded in Minecraft.
Additionally, we are currently unable to synthesize sequential circuits, aka any circuits with a loopback or feedback. That means no memory, no counters or any circuit that could hold a state.
MinecraftHDL is an educational tool to illustrate on a macro-scopic scale how microelectronic digital circuits are designed and produced. It is a great way to introduce younger audiences to the world of digital design and can also be used to illustrate the difference between software and hardware design to undergraduate engineers taking their first RTL class.
Supervisor: Brett H. Meyer - [Website](http://rssl.ece.mcgill.ca/~bhm/)
Students: Francis O'Brien - [Website](http://francisobrien.com)
Omar Ba Mashmos
Andrew Penhale
A 2-bit 7-segment display decoder in action (the display itself was not generated by MinecraftHDL)
---
To show how easy it is to make a circuit with MinecraftHDL here is a gif of me creating a circuit, synthesizing, and generating it in minecraft in less than a minute!
The circuit I generate above is a 2bit adder. It takes two numbers of two bits and adds them. At the end of the gif I set both input numbers to '11' which is the binary representation of the number 3. Then I move to the output and we see that O3=1, O2=1, and O1=0, this gives the binary number '110' which is indeed 6.