https://github.com/itsfrank/MinecraftHDL

A Verilog synthesis flow for Minecraft redstone circuits
https://github.com/itsfrank/MinecraftHDL

Last synced: 2 months ago
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A Verilog synthesis flow for Minecraft redstone circuits

• Host: GitHub
• URL: https://github.com/itsfrank/MinecraftHDL
• Owner: itsfrank
• Created: 2016-10-05T00:44:38.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2020-11-25T20:09:40.000Z (about 4 years ago)
• Last Synced: 2024-08-03T01:39:31.226Z (6 months ago)
• Language: SystemVerilog
• Homepage:
• Size: 67.3 MB
• Stars: 1,101
• Watchers: 17
• Forks: 24
• Open Issues: 10
• Metadata Files:
  • Readme: README.md

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