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https://github.com/ivanmilin/riscv_multicore_cache_controller

This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
https://github.com/ivanmilin/riscv_multicore_cache_controller

assembly formal-verification jasper-gold multicore-cpu ripes risc-v singlecycle-processor systemverilog

Last synced: about 2 months ago
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This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.

Host: GitHub
URL: https://github.com/ivanmilin/riscv_multicore_cache_controller
Owner: ivanMilin
Created: 2024-09-02T11:38:24.000Z (5 months ago)
Default Branch: main
Last Pushed: 2024-12-16T12:44:56.000Z (about 2 months ago)
Last Synced: 2024-12-16T13:54:27.779Z (about 2 months ago)
Topics: assembly, formal-verification, jasper-gold, multicore-cpu, ripes, risc-v, singlecycle-processor, systemverilog
Language: SystemVerilog
Homepage:
Size: 12.8 MB
Stars: 3
Watchers: 1
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: README.md

        System overview :

![top_module](https://github.com/user-attachments/assets/797874b8-bdf8-472e-bbbd-0521b15bd7ab)