https://github.com/izyasoft/easyhdllib

A coocbook of HDL (primarily Verilog) modules
https://github.com/izyasoft/easyhdllib

altera clock-divider fifo fpga frequencies frequency-analysis hdl verilog verilog-components verilog-hdl verilog-library verilog-snippets xilinx-fpga

Last synced: about 1 month ago
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A coocbook of HDL (primarily Verilog) modules

• Host: GitHub
• URL: https://github.com/izyasoft/easyhdllib
• Owner: IzyaSoft
• License: gpl-3.0
• Created: 2016-10-09T14:14:58.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2017-04-24T19:48:44.000Z (almost 8 years ago)
• Last Synced: 2023-03-09T00:58:00.981Z (almost 2 years ago)
• Topics: altera, clock-divider, fifo, fpga, frequencies, frequency-analysis, hdl, verilog, verilog-components, verilog-hdl, verilog-library, verilog-snippets, xilinx-fpga
• Language: Verilog
• Size: 315 KB
• Stars: 5
• Watchers: 5
• Forks: 0
• Open Issues: 0

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