https://github.com/izyasoft/easyhdllib
A coocbook of HDL (primarily Verilog) modules
https://github.com/izyasoft/easyhdllib
altera clock-divider fifo fpga frequencies frequency-analysis hdl verilog verilog-components verilog-hdl verilog-library verilog-snippets xilinx-fpga
Last synced: 7 months ago
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A coocbook of HDL (primarily Verilog) modules
- Host: GitHub
- URL: https://github.com/izyasoft/easyhdllib
- Owner: IzyaSoft
- License: gpl-3.0
- Created: 2016-10-09T14:14:58.000Z (about 9 years ago)
- Default Branch: master
- Last Pushed: 2017-04-24T19:48:44.000Z (over 8 years ago)
- Last Synced: 2025-02-12T21:15:36.482Z (9 months ago)
- Topics: altera, clock-divider, fifo, fpga, frequencies, frequency-analysis, hdl, verilog, verilog-components, verilog-hdl, verilog-library, verilog-snippets, xilinx-fpga
- Language: Verilog
- Size: 315 KB
- Stars: 6
- Watchers: 5
- Forks: 0
- Open Issues: 0