https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.
https://github.com/jackson-nestelroad/verilog-mips-processor

cpu mips processor verilog

Last synced: 12 days ago
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Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

• Host: GitHub
• URL: https://github.com/jackson-nestelroad/verilog-mips-processor
• Owner: jackson-nestelroad
• Created: 2021-04-26T16:09:52.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2021-05-03T16:54:50.000Z (almost 4 years ago)
• Last Synced: 2024-12-01T07:44:17.379Z (2 months ago)
• Topics: cpu, mips, processor, verilog
• Language: SystemVerilog
• Homepage:
• Size: 15.6 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Verilog MIPS Processor

This repository features my final project for CS 4341: Digital Logic and Computer Design. I implemented a single-cycle processor that executes a small subset of 32-bit MIPS instructions.

Instructions are not stored and fetched in an instruciton memory unit. Instead, they are continuously fed to the processor through an input port. Thus, no branching instructions are supported.

This processor supports several R-format instructions, arithmetic I-format instructions, and memory word instructions.

## Running in ModelSim

I simulated this project using ModelSim. I have documented the process for running this project below.

1. Open a command-line terminal at the base directory of the project, which is where "test-bench.sv" is located.

2. Run `vsim` to start ModelSim. The following commands take place inside ModelSim.

3. Run `vlib work` to create a work library.

4. Run `vlog test-bench.sv` to compile the project.

5. Run `vsim work.TestBench` to begin a simulation.

6. Run `run -all` inside the simulation to run the entire simulation.

7. If compiled and run correctly, all tests should be displayed as passing.