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https://github.com/jackson-nestelroad/verilog-mips-processor
Single-cycle 32-bit MIPS processor implemented in SystemVerilog.
https://github.com/jackson-nestelroad/verilog-mips-processor
cpu mips processor verilog
Last synced: about 1 month ago
JSON representation
Single-cycle 32-bit MIPS processor implemented in SystemVerilog.
- Host: GitHub
- URL: https://github.com/jackson-nestelroad/verilog-mips-processor
- Owner: jackson-nestelroad
- Created: 2021-04-26T16:09:52.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2021-05-03T16:54:50.000Z (over 3 years ago)
- Last Synced: 2024-10-15T18:25:33.469Z (3 months ago)
- Topics: cpu, mips, processor, verilog
- Language: SystemVerilog
- Homepage:
- Size: 15.6 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0