https://github.com/jakubcabal/sdram-tester-fpga
SDRAM Tester implemented in FPGA
https://github.com/jakubcabal/sdram-tester-fpga
cyc1000 fpga measures-throughput python sdram sdram-controller sdram-tester vhdl
Last synced: 9 months ago
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SDRAM Tester implemented in FPGA
- Host: GitHub
- URL: https://github.com/jakubcabal/sdram-tester-fpga
- Owner: jakubcabal
- License: mit
- Created: 2020-10-24T14:57:54.000Z (over 5 years ago)
- Default Branch: main
- Last Pushed: 2021-05-01T09:32:28.000Z (about 5 years ago)
- Last Synced: 2023-03-03T02:11:17.255Z (over 3 years ago)
- Topics: cyc1000, fpga, measures-throughput, python, sdram, sdram-controller, sdram-tester, vhdl
- Language: VHDL
- Homepage:
- Size: 60.5 KB
- Stars: 7
- Watchers: 2
- Forks: 1
- Open Issues: 0