https://github.com/jakubcabal/uart-for-fpga
Simple UART controller for FPGA written in VHDL
https://github.com/jakubcabal/uart-for-fpga
controller cyc1000 fpga ghdl simulation uart uart-controller uart-loopback vhdl wishbone wishbone-bus
Last synced: about 1 month ago
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Simple UART controller for FPGA written in VHDL
- Host: GitHub
- URL: https://github.com/jakubcabal/uart-for-fpga
- Owner: jakubcabal
- License: mit
- Created: 2015-07-24T17:02:42.000Z (about 10 years ago)
- Default Branch: master
- Last Pushed: 2021-08-07T09:55:26.000Z (about 4 years ago)
- Last Synced: 2023-03-03T02:11:17.403Z (over 2 years ago)
- Topics: controller, cyc1000, fpga, ghdl, simulation, uart, uart-controller, uart-loopback, vhdl, wishbone, wishbone-bus
- Language: VHDL
- Homepage:
- Size: 97.7 KB
- Stars: 65
- Watchers: 10
- Forks: 23
- Open Issues: 1