https://github.com/jamesits/verilog-basic-blocks

数电作业
https://github.com/jamesits/verilog-basic-blocks

verilog verilog-components xilinx-ise

Last synced: 29 days ago
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数电作业

• Host: GitHub
• URL: https://github.com/jamesits/verilog-basic-blocks
• Owner: Jamesits
• Created: 2017-12-30T06:09:39.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2018-01-11T09:15:04.000Z (almost 7 years ago)
• Last Synced: 2024-04-14T07:45:30.978Z (7 months ago)
• Topics: verilog, verilog-components, xilinx-ise
• Language: Verilog
• Size: 120 KB
• Stars: 2
• Watchers: 3
• Forks: 1
• Open Issues: 0

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