https://github.com/jameslzhu/riscv-card
An unofficial assembly reference for RISC-V.
https://github.com/jameslzhu/riscv-card
asm berkeley isa latex reference riscv
Last synced: 3 months ago
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An unofficial assembly reference for RISC-V.
- Host: GitHub
- URL: https://github.com/jameslzhu/riscv-card
- Owner: jameslzhu
- License: cc-by-4.0
- Created: 2017-10-04T19:14:11.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2024-11-12T01:12:39.000Z (over 1 year ago)
- Last Synced: 2025-03-26T17:42:24.274Z (about 1 year ago)
- Topics: asm, berkeley, isa, latex, reference, riscv
- Language: TeX
- Homepage:
- Size: 524 KB
- Stars: 478
- Watchers: 18
- Forks: 59
- Open Issues: 2
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# RISC-V Reference Card
An unofficial reference sheet for RISC-V, the free and libre instruction set from Berkeley. ([**PDF**][pdf]).
## Compiling
Compile the root document `riscv-card.tex` with [LaTeX][latex] from your system's
standard TeX distribution (TeX Live / MikTeX):
```sh
pdflatex riscv-card.tex
```
Or with [tectonic][tectonic]:
```sh
tectonic riscv-card.tex
```
## What's inside?
- The base 32-bit ISA (RV32I), with opcode values and C-like descriptions
- Standard ISA extensions (currently only targeting the RVI20 standard profile)
- Register aliases and calling conventions
- Pseudoinstructions
Other information from the more official reference cards not specific to the
ISA, like the stack/heap memory layout, IEEE 754 floating-point layout, and size
prefixes, have been omitted.
## Why?
In RISC tradition, the assembly reference for [MIPS][mips-green-sheet]
and [RISC-V][riscv-card] fits onto a single double-sided 'Green Sheet'.
When I took [CS 61C][cs61c] at UC Berkeley in 2017, we were the first semester taught
using RISC-V, and our reference card scans from our [RISC-V textbook][patterson-hennessy]
were low-quality. I wanted a card I didn't have to squint at, so I typeset it in LaTeX.
This little reference has grown well past a double-sided page, but if you still want
the original you can print the first and last pages for the asm opcodes and calling convention.
## Contributing
This repository is not actively developed, but pull requests are accepted for
fixes, new ISA standard extensions, style improvements, or other such changes.
Please include a rebuilt PDF binary in your pull request.
Print-friendly format is preferred, when possible: legible font sizes, clean
page breaks and full letter page width usage.
(A4 support may be a good thing to check.)
Some ideas if you are truly motivated:
- RISCV64 64-bit ISA support
- Directly parsing the spec, banishing typos forever
- Build system to select binary or hex instruction opcodes
## Licensing
This work is licensed under the Creative Commons [CC-BY-4.0][CC] license.
(See LICENSE for the full text.)
In brief, feel free to use this for your own purposes, as long as you credit
me, and don't restrict others. (Again, read the license for the specifics.)
This work is adapted from the RISC-V Instruction Set Manual, available at
[https://riscv.org/specifications/][RV] and licensed
under the Creative Commons [CC-BY-4.0][CC] license.
[pdf]: https://github.com/jameslzhu/riscv-card/releases/download/latest/riscv-card.pdf
[RV]: https://riscv.org/specifications "RISC-V spec"
[CC]: https://creativecommons.org/licenses/by/4.0/ "CC-BY-4.0"
[cs61c]: https://cs61c.org/
[patterson-hennessy]: https://www.elsevier.com/books/catalog/isbn/9780128203316
[riscv-card]: https://inst.eecs.berkeley.edu/~cs61c/resources/RISCV_Green_Sheet.pdf
[mips-green-sheet]: https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_Green_Sheet.pdf
[latex]: https://www.latex-project.org/get/
[tectonic]: https://tectonic-typesetting.github.io/en-US/