https://github.com/jamieiles/oldland-cpu

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
https://github.com/jamieiles/oldland-cpu

Last synced: 2 months ago
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Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

• Host: GitHub
• URL: https://github.com/jamieiles/oldland-cpu
• Owner: jamieiles
• Created: 2013-07-03T17:14:38.000Z (over 11 years ago)
• Default Branch: master
• Last Pushed: 2016-02-19T18:30:21.000Z (almost 9 years ago)
• Last Synced: 2024-08-03T01:39:45.746Z (6 months ago)
• Language: Verilog
• Homepage: http://jamieiles.github.io/oldland-cpu
• Size: 1.17 MB
• Stars: 119
• Watchers: 17
• Forks: 21
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

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README

        
Oldland CPU

===========

[![Build Status](https://travis-ci.org/jamieiles/oldland-cpu.svg?branch=master)](https://travis-ci.org/jamieiles/oldland-cpu)

Oldland is a 32-bit RISC CPU targeted at FPGAs.  The main features are:

  - 5 stage load/store pipeline.

  - 16 general purpose registers.

  - N-way set-associative blocking instruction/data caches

  - Software managed instruction/data TLBs with 4KB page size.

  - JTAG debug controller for execution control and state

  modification/inspection.

  - Exception table for interrupts, data/instruction aborts, illegal

  instruction and software interrupts along with separate ITLB/DTLB miss

  handlers.

  - User and supervisor modes.

Keynsham is a SoC using Oldland as the core and has a number of peripherals:

 - 32MB SDR SDRAM controller.

 - SPI master with configurable number of chip selects.

 - On-chip bootrom.

 - On-chip memory.

 - Programmable timers.

 - Interrupt controller.

 - UART.

 - SPI master.

 - GPIO.

There is a C model along with Icarus and Verilator RTL simulations.  The

Keynsham SoC can be synthesized to run on a Terasic DE0 Nano or DE0-CV.  There

are ports of binutils, gcc and u-boot available.

For documentation see the [Oldland CPU site](http://jamieiles.github.io/oldland-cpu/)