https://github.com/jarircse16/verilog_practice

Sample Verilog Codes
https://github.com/jarircse16/verilog_practice

Last synced: about 9 hours ago
JSON representation

Sample Verilog Codes

• Host: GitHub
• URL: https://github.com/jarircse16/verilog_practice
• Owner: jarircse16
• Created: 2023-09-23T20:46:38.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2023-09-23T20:47:49.000Z (about 1 year ago)
• Last Synced: 2023-09-24T01:30:10.331Z (about 1 year ago)
• Language: Verilog
• Size: 2.93 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project