https://github.com/jasonbrave/jasonbrave

GitHub profile
https://github.com/jasonbrave/jasonbrave

Last synced: 5 months ago
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GitHub profile

• Host: GitHub
• URL: https://github.com/jasonbrave/jasonbrave
• Owner: JasonBrave
• Created: 2021-11-21T20:25:32.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2025-05-12T14:10:15.000Z (about 1 year ago)
• Last Synced: 2025-05-12T15:29:39.951Z (about 1 year ago)
• Size: 11.7 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
### Hi there 👋, My name is Jason Xu

- 😄 Pronouns: He/Him

- I'm a third-year Computer Engineering student at University of Waterloo

- I enjoy working on ASIC and FPGA designs with SystemVerilog

- I also enjoy low-level programming and systems programming, including device driver and firmware development, and operating system kernel development

- I design PCB with KiCAD

## Programming languages that I use:

- C

- C++

- Rust

- x86 and RISC-V Assembly Language

## Hardware description languages that I use:

- Verilog

- SystemVerilog

- VHDL

![](https://github-readme-stats.vercel.app/api?username=JasonBrave&show_icons=true&count_private=true&role=OWNER,COLLABORATOR,ORGANIZATION_MEMBER)

![](https://github-readme-stats.vercel.app/api/top-langs/?username=JasonBrave&layout=compact&langs_count=10&role=OWNER,COLLABORATOR)