https://github.com/jasonbrave/pci-edu

SystemVerilog implemention of QEMU PCI edu device
https://github.com/jasonbrave/pci-edu

pci pci-bus pci-devices systemverilog verilator verilog

Last synced: 19 days ago
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SystemVerilog implemention of QEMU PCI edu device

• Host: GitHub
• URL: https://github.com/jasonbrave/pci-edu
• Owner: JasonBrave
• License: gpl-3.0
• Created: 2021-12-04T00:16:56.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2023-05-22T16:07:13.000Z (over 1 year ago)
• Last Synced: 2024-11-09T12:12:19.577Z (about 2 months ago)
• Topics: pci, pci-bus, pci-devices, systemverilog, verilator, verilog
• Language: SystemVerilog
• Homepage:
• Size: 56.6 KB
• Stars: 10
• Watchers: 1
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: COPYING

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README

        
# PCI Edu device

This is an attempt to implement [QEMU PCI Edu device](https://github.com/qemu/qemu/blob/master/docs/specs/edu.txt) in SystemVerilog.

PCI Vendor ID 0x1234, Device ID 0x11e8.

### Features planned to implement

* PCI Bus

* PCI configuration space

* Memory address decoder

* Line interrupt and MSI interrupt

* MMIO registers

* Bus mastering DMA

### Getting started

Simulating PCI Edu device requires G++, make and Verilator. A VCD waveform viewer is also required for viewing waveform.\

Run simulation: `make sim`

### Source structure

`rtl` SystemVerilog RTL source code\

`tb/edu_verilator_wrapper.sv` SystemVerilog verilator wrapper, used as top level module for verilator simulation\

`sim_main.cpp` Verilator C++ testbench